1. Field of the Invention
The present invention relates to a method and an apparatus for controlling the direction of data transfer on a data bus in a system having the ability to effect direct memory access (hereinafter referred to as DMA).
2. Description of the Prior Art
FIG. 1 schematically shows the setup of a conventional data processing system having DMA transfer, comprising a central processing unit (hereinafter referred to as CPU) 1, a main memory 2, a DMA controller for 3 for controlling the DMA transfer, and an input/output controller 4 for controlling data transfer for an input/output device 5, wherein the data is transferred among these devices through a data bus 6 and an address bus (not shown). Although these devices are controlled via control buses, the drawing shows only one signal line among them, i.e. it shows only a read-out/write-in control line (hereinafter called R/W control line) 7 for determining the direction of transferring the data.
In order to transfer data between main memory 2 and input/output controller 4, a program controlled I/O (PCIO) transfer mode may be employed being controlled by the program of the CPU 1. The data may also be directly transferred between the main memory 2 and the input/output controller 4 independent of the control of the CPU 1, based upon the DMA transfer mode. In these two cases, the above-mentioned R/W control line 7 can be commonly employed even in the PCIO transfer mode or the DMA transfer mode. Therefore, in order to use the R/W control line 7 for the DMA transfer mode, the signal levels of the R/W control line 7 produced by the DMA controller 3 must be set at conflicting levels by some means depending upon the main memory 2 and the input/output controller 4. For instance, when the DMA controller 3 has sent a high level control signal (H level) to th R/W control line 7, and when the main memory 2 has recognized it as the H level, the input/output controller 4 must recognize it as the low level (L level). The reason is because the main memory 2 and the input/output controller 4 must determine without interfering the direction of data transfer from the main memory 2 to the input/output controller 4 or the direction of data transfer from the input/output controller 4 to the main memory 2. Under the DMA transfer mode, the input/output controller 4 usually recognizes the signal level of the R/W control line 7 as inverted.
FIG. 2 shows the setup of a circuit of part of a conventional input/output controller 4, or in other words, it shows a portion of a control circuit for controlling the direction of data transfer of the data bus under the DMA transfer mode.
In FIG. 2, reference numeral 21 represents a flip-flop that will be set in the DMA transfer mode (hereinafter referred to as DMA-FF), reference numerals 22 and 23 denote AND gates, 24 a wired OR gate, 25 and 26 inverters, 27 a data bus buffer for transferring data from the data bus 6 toward the input/output controller 4, 28 a data bus buffer for transferring the data from the input/output controller 4 toward the data bus 6, 29 an input register, and reference numeral 30 designates an output register.
FIG. 3 is a timing chart for illustrating the operation of the circuit of FIG. 2, in which the diagram (a) represents an output from the terminal Q of the DMA-FF 21, the diagram (b) represents a read-out/write-in control signal (hereinafter referred to as R/W control signal) of the R/W control line 7, the diagram (c) represents an output of the inverter 25, diagram (d) represents an output of the wired OR gate 24, and the diagram (e) shows the state of controlling the direction of data transfer using the data bus buffers 27 and 28. In the diagram (e) of FIG. 3, symbol A shows the state in which the data bus buffers 28 is driven, i.e. the state in which data is transferred from the input/output controller 4 toward the data bus 6, and B shows the state in which the data bus buffer 27 is driven, i.e. the state in which the data is transferred from the data bus 6 toward the input/output controller 4.
Referring to FIG. 2, before DMA transfer commences, the DMA-FF 21 is set by a control signal from the CPU 1 of FIG. 1, whereby a predetermined amount of data is transferred. After DMA transfer is finished, the DMA-FF 21 is reset by a control signal from the CPU 1 or by a signal of the input/output controller 4. While the DMA-FF 21 is being set, i.e. during the DMA transfer mode, the output of the terminal Q of the DMA-FF 21 goes high (H level) as shown by the diagram (a) of FIG. 3, whereby AND gate 23 is enabled, and a signal obtained by inverting the R/W control signal of the R/W control line 7 through the inverter 25 is applied to the wired OR gate 24, such that the R/W control signal is recognized. On the other hand, under ordinary PCIO transfer mode in which the DMA-FF 21 is reset, the Q output of the DMA-FF 21 goes high (H level), whereby AND gate 22 is enabled, and the R/W control signal is directly applied to the wired OH gate 24.
Therefore, if the R/W control signal shown by the diagram (b) of FIG. 3 is applied to the R/W control line 7, the output of the inverter 25 acquires the form as shown in the diagram (c) of FIG. 3. Consequently, the output of the wired OR gate 24 acquires the form as shown in the diagram (d) of FIG. 3, and the main bus buffers 27 and 28 are controlled as shown in the diagram (e) of FIG. 3 thereby to control the direction of data transfer.
Here, the DMA transfer mode may be divided into a transfer in burst mode in which the data bus is seized during the period of DMA transfer, and a transfer in cycle steal mode which performs the transfer of data in parallel with the program processing using the CPU during the period of DMA transfer. When the above-mentioned conventional control method is being put into practice, the transfer in burst mode presents no problem since it seizes the bus. However, with the transfer in cycle steal mode in which the transfer of data and the processing of program are performed in parallel, the conventional system which recognizes the R/W control signal throughout the period of DMA transfer mode had to produce the R/W control signal when the CPU was to access the input/output controller during the period of program processing due to any requirement and when the programs were being processed. Consequently, the program necessitated mode control. This mode control was needed for determining the access direction to the input/output controller depending upon whether the DMA mode is taking place or not. Eventually, program design tended to become very cumbersome.